Delaying all incoming signals by 2 ms using VHDL

You might find this discussion valuable (http://zipcpu.com/dsp/2017/11/10/delayw.html), http://zipcpu.com/dsp/2017/11/10/delayw.html (http://zipcpu.com/dsp/2017/11/10/delayw.html), it describes how to build a delay line--just what you are looking for. The only difficulty is that the discussion revolves around a varilog implementation. Still, I think you'll find some valuable points to work from there.