Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorDelaying all incoming signals by 2 ms using VHDL
Hi to all, I'm a finance student and I'm also interested in electronics, these days I do program because my limited of knowledge of this, so ask for help in here.I have two incoming signals that I wa...
Altera_ForumHonored Contributor
Honored ContributorYou might find this discussion valuable (http://zipcpu.com/dsp/2017/11/10/delayw.html), http://zipcpu.com/dsp/2017/11/10/delayw.html (http://zipcpu.com/dsp/2017/11/10/delayw.html), it describes how to build a delay line--just what you are looking for. The only difficulty is that the discussion revolves around a varilog implementation. Still, I think you'll find some valuable points to work from there.
Dan
