delay a signal by several clk cycles in verilog

Question

Hi,

Is there anyone knows an easier way to delay a signal by several clk cycles in verilog

I was trying to use repeat as below, however, it only works when I run RTL simulation, it will not work when I run gate level simulation.

data_out <= repeat (15) @(posedge clk ) data;

Thanks!!

altera_forum · Answer

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Hi,

Is there anyone knows an easier way to delay a signal by several clk cycles in verilog

I was trying to use repeat as below, however, it only works when I run RTL simulation, it will not work when I run gate level simulation.

data_out <= repeat (15) @(posedge clk ) data;

Thanks!!

--- Quote End ---

It's called a SHIFT REGISTER. Google: shift register verilog code

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