Decrypt problem in std version of Quartus

Hi,

I am having problems to decrypt some Verilog files in Quartus std version vq18.1 that have been encrypted using Quartus pro version vq18.1p.

Since it is not possible to encrypt using the standard version, I thought that decryption would always be possible because it is an IEEE standard.

The error message I am receiving is:

Critical Warning (10191): Verilog HDL Compiler Directive warning at file1.v(1): text macro "pragma" is undefined File: /test/file1.v Line: 1 

Error (10170): Verilog HDL syntax error at file1.v(2) near text: "protect"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /test/file1.v Line: 2 

The content of the file where it complains about is:

`pragma protect begin_protected 
`pragma protect version=1 
`pragma protect author="Intel Corporation" 
`pragma protect encrypt_agent="Quartus Prime Pro Software" 
`pragma protect encrypt_agent_info="17.1" 

For the encryption I used the following command:

./path_to_quartus/bin/encrypt_1735 --quartus --simulation=mentor --language=vhdl /path_to_file/file.v 

I have already seen some post talking about this issue:

4.13. Support for the IEEE 1735 Encryption Standard (intel.com)

Solved: IEEE 1735 Encryption Public Key - Intel Community

In the last one also mentioning another tools to perform the decryption task "Ampcrypt/Amplic tool".

Now I am a bit confused about how I can solve this problem, could you help me further?

Thanks!