DE0-Nano-Programming

Try this:

-- KEY0 - PIN_J15
-- LED0 - PIN_A15
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY Test IS
	PORT
	(
		KEY0	: IN	STD_LOGIC;
		LED0	: OUT	STD_LOGIC
	);
END Test;
ARCHITECTURE a OF Test IS
BEGIN
	LED0 <= KEY0;
END a;

There is a 50 MHz incoming clock on the DE-Nano. I suggest dividing this down to 1 MHz with the PLL megafunction, then creating a 3 Hz tick signal from the 1 MHz clock. Then drive all eight LEDS with this 3 Hz heartbeat signal, alternating with the logical not every other LED. In this way, you can really see that the logic in the FPGA is fundamentally working, and all LED's are okay.

	/*----------------------------------------------
	   LED Outputs
	----------------------------------------------*/	
	LED_OUT(0) <= hb_led;
	LED_OUT(1) <= not(hb_led);
	LED_OUT(2) <= hb_led;
	LED_OUT(3) <= not(hb_led);
	LED_OUT(4) <= hb_led;
	LED_OUT(5) <= not(hb_led);
	LED_OUT(6) <= hb_led;
	LED_OUT(7) <= not(hb_led);

Thanks, i copied and paste into my quartus window, but its showing error like

You need to look for the actual error message. It should be further up in the log window, and you can't miss it, it will be in red.

I've attached my project. You should be able to build it.