DE0-Nano-Programming

There is a 50 MHz incoming clock on the DE-Nano. I suggest dividing this down to 1 MHz with the PLL megafunction, then creating a 3 Hz tick signal from the 1 MHz clock. Then drive all eight LEDS with this 3 Hz heartbeat signal, alternating with the logical not every other LED. In this way, you can really see that the logic in the FPGA is fundamentally working, and all LED's are okay.

	/*----------------------------------------------
	   LED Outputs
	----------------------------------------------*/	
	LED_OUT(0) <= hb_led;
	LED_OUT(1) <= not(hb_led);
	LED_OUT(2) <= hb_led;
	LED_OUT(3) <= not(hb_led);
	LED_OUT(4) <= hb_led;
	LED_OUT(5) <= not(hb_led);
	LED_OUT(6) <= hb_led;
	LED_OUT(7) <= not(hb_led);