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Altera_Forum's avatar
Altera_Forum
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11 years ago

DDR3 with Uniphy on Cyclone V

Hi,

I'm trying to interface a DDR3 memory with UNIPHY with a custom component in QSYS. After successful generation of the HDL files, Analysis and synthesis was done which was successful.

The <>_pin_assignments.tcl script was run and errors were seen. I have attached the log file of the errors.

Due to this, Place and fitter had hundreds of the following error:

Error (174068): Output buffer atom "system_DDR3_Memory:ddr3_memory|system_DDR3_Memory_p0:p0|system_DDR3_Memory_p0_memphy:umemphy|system_DDR3_Memory_p0_new_io_pads:uio_pads|system_DDR3_Memory_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_cyclonev:altdq_dqs2_inst|pad_gen[3].data_out" has port "PARALLELTERMINATIONCONTROL[5]" connected, but does not use calibrated on-chip termination

I'm using a Cyclone V SX SoC device with Quartus 14.1 version.

Please let me know if I'm missing something.

Thanks and Regards,

Nitin.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    This error was solved. Having a common clock would cause this. Since the same clock was reused, the PLL in the FPGA was not able to provide a stable clock causing this problem. Once the clocks were separated, the issue was resolved.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi nitin003,

    My name is hung.

    I'm now trying to use DDR3 as a buffer and I want use DDR3 controller with UniPHY in Qsys. Cauz I'm a newbie, I don't know how to configure the parameters, where can I get the information to configure them.

    Regards

    Hung