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Altera_Forum
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11 years ago

DDR3 with Uniphy on Cyclone V

Hi, I'm trying to interface a DDR3 memory with UNIPHY with a custom component in QSYS. After successful generation of the HDL files, Analysis and synthesis was done which was successful. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

This error was solved. Having a common clock would cause this. Since the same clock was reused, the PLL in the FPGA was not able to provide a stable clock causing this problem. Once the clocks were separated, the issue was resolved.