Forum Discussion
MPaso
New Contributor
New ContributorDDR3 burst size
Hello everybody I have a system with CYCLONE V and DDR3 2Gbit memory (16bit data bus and 14 bit address bus). The DDR3 is connected to HMC pins of the FPGA. When i go to the UniPHY memory DDR3 compo...
MPasoNew Contributor
New ContributorThank you for the answer.
Can you or anybody else then further elaborate how are Avalon burst length and DDR3 external memory burst length related.
When i read the datasheet of the DDR3 the BL is 8. Then there is also the issue of address boundary. Since I wrote my own mm master to write/read to and from DDR3 in this case does it mean that i have to only provide an address and burst length to UniPHY and all the correct addressing and data access will be automatically arranged or do i have to make sure that boundary addressing is handled correctly and every 8 access (assuming DDR BL) my mm master must update the address?
Thank you
