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Altera_Forum's avatar
Altera_Forum
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8 years ago

DDR2_SDRAM Interface to Cyclone-3 device

Hi

I have downloaded this attached code.

This code pin assignment is not matching with our board pin assignment, so I just removed the .qsf file and run again to do the pin assignment as per our board.

there is no error in : analysis & synthesis, fitter, assembler, timequest timing analyser phase

but we got error in : eda netlist generator phase.

Error what I got also attached here.

Please guide us how to go ahead.

Error is listed here:

Error: Can't generate netlist output files because the file "H:/jk_2017/VHDL_CODE_LEARNING/level_2/DDR_DOWNLOAD_CODE/CIII_DDR2_restored/auk_ddr_hp_controller.vhd" is an OpenCore Plus time-limited file

Error: Can't generate netlist output files because the license for encrypted file "H:/jk_2017/VHDL_CODE_LEARNING/level_2/DDR_DOWNLOAD_CODE/CIII_DDR2_restored/auk_ddr_hp_controller.vhd" is not available

Error: Can't generate netlist output files because the file "H:/jk_2017/VHDL_CODE_LEARNING/level_2/DDR_DOWNLOAD_CODE/CIII_DDR2_restored/auk_ddr_hp_controller.vhd" is an OpenCore Plus time-limited file

Error: Can't generate netlist output files because the license for encrypted file "H:/jk_2017/VHDL_CODE_LEARNING/level_2/DDR_DOWNLOAD_CODE/CIII_DDR2_restored/auk_ddr_hp_controller.vhd" is not available

Error: Can't generate netlist output files because the file "H:/jk_2017/VHDL_CODE_LEARNING/level_2/DDR_DOWNLOAD_CODE/CIII_DDR2_restored/auk_ddr_hp_controller.vhd" is an OpenCore Plus time-limited file

Error: Can't generate netlist output files because the license for encrypted file "H:/jk_2017/VHDL_CODE_LEARNING/level_2/DDR_DOWNLOAD_CODE/CIII_DDR2_restored/auk_ddr_hp_controller.vhd" is not available

Error: Can't generate netlist output files because the file "H:/jk_2017/VHDL_CODE_LEARNING/level_2/DDR_DOWNLOAD_CODE/CIII_DDR2_restored/auk_ddr_hp_controller.vhd" is an OpenCore Plus time-limited file

Error: Can't generate netlist output files because the license for encrypted file "H:/jk_2017/VHDL_CODE_LEARNING/level_2/DDR_DOWNLOAD_CODE/CIII_DDR2_restored/auk_ddr_hp_controller.vhd" is not available

Error: Quartus II EDA Netlist Writer was unsuccessful. 8 errors, 0 warnings

Error: Peak virtual memory: 275 megabytes

Error: Processing ended: Thu Jun 15 12:50:18 2017

Error: Elapsed time: 00:01:26

Error: Total CPU time (on all processors): 00:00:01

Error: Quartus II Full Compilation was unsuccessful. 10 errors, 139 warnings

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    The EDA netlist writer is the final stage of the compiler used to generate files for third-party tools, such as a simulator. The error is due to the fact that your DDR2 IP is not licensed, which is strange because this IP is part of the IP base suite included with Quartus. Are you using the Lite or older Web edition of the software?

    In any case, if you don't need files for a third-party tool, the .sof file generated from this compilation will still work fine in hardware as long as you leave JTAG connected to your board.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    This mean you do not have official license for the IP core, you can contact you local FAE to get the license for this IP and compile is without error. Otherwise, as recommend by sstrell, you have to connect the JTAG when validating or using the IP.

    (This message was posted on behalf of Intel Corporation)