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Altera_Forum
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15 years ago

DDR2 memory design failed

Generated a test case from external memory IP for DDR2 design, When I ran the design in QuartusII, it is giving error message as follows, Can some help me with the case...I looked into the Altera Web but i couldn't find solution.

Error: Cannot place pin mem_clk[0] to location J16

Error: Can't place VREF pin L14 (VREFGROUP_B5_N0) for pin mem_clk[0] of type bi-directional with SSTL-18 Class I I/O standard at location J16

Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 5 when the VREF pin L14 (VREFGROUP_B5_N0) is used on device EP3C10F256C7 -- no more than 9 output/bidirectional pins within 14 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 12 pins driving out.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    It seems you designed the pcb yourself, may be you have to redesign it.

    The SSTL-18 IO can not be used freely as you want, the numbers in each bank you can use are limited.

    Refer to chapter 8 in Cyclone III Device Handbook Volume 1, especially Table 8–5 and related descriptions.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi loywong,

    thanks for your feedback, But I couldn't find table 8-5 in cyclone III handbook. It seems that the table is removed in latest version of Document. Can you point me to exact table number. I assume it is 8-1/8-2 which describes about Cyclone III/Cyclone III LS Device DQS and DQ Bus Mode Support for Each Side of the Device. But I am following all the rules mentioned in that table.

    Here I am attaching the QSF you can have a look.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Oh, you are right, it is table 8-1 now, my handbook is out of date.

    In you qsf file:

    --- Quote Start ---

    set_location_assignment PIN_L14 -to mem_addr[12]

    --- Quote End ---

    you can not use L14 as an IO, it is the REFERENCE VOLTAGE INPUT for VREFB5. SSTL is a kind of persudo differential IO standard, a group of SSTL io must have a common reference voltage. You must connect it to a 0.9V voltage source for you are using the VREFB5 group(some of your DQ, DQS, ADDR... are SSTL IOs in this group).

    Anothor thing I found:

    --- Quote Start ---

    set_location_assignment PIN_J16 -to mem_clk[0]

    set_location_assignment PIN_K16 -to mem_clk_n[0]

    --- Quote End ---

    while in 3C10's pin-outs file they are:

    DIFFIO_R7n

    DIFFIO_R8n

    not a differential pair.

    I think you shoud place them in a same differential pair.