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Altera_Forum
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15 years ago

DDR2 memory design failed

Generated a test case from external memory IP for DDR2 design, When I ran the design in QuartusII, it is giving error message as follows, Can some help me with the case...I looked into the Altera Web...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi loywong,

thanks for your feedback, But I couldn't find table 8-5 in cyclone III handbook. It seems that the table is removed in latest version of Document. Can you point me to exact table number. I assume it is 8-1/8-2 which describes about Cyclone III/Cyclone III LS Device DQS and DQ Bus Mode Support for Each Side of the Device. But I am following all the rules mentioned in that table.

Here I am attaching the QSF you can have a look.