Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

DDR2 memory design failed

Generated a test case from external memory IP for DDR2 design, When I ran the design in QuartusII, it is giving error message as follows, Can some help me with the case...I looked into the Altera Web...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

It seems you designed the pcb yourself, may be you have to redesign it.

The SSTL-18 IO can not be used freely as you want, the numbers in each bank you can use are limited.

Refer to chapter 8 in Cyclone III Device Handbook Volume 1, especially Table 8–5 and related descriptions.