DDR2 memory design failed

Oh, you are right, it is table 8-1 now, my handbook is out of date.

In you qsf file:

--- Quote Start ---

set_location_assignment PIN_L14 -to mem_addr[12]

--- Quote End ---

you can not use L14 as an IO, it is the REFERENCE VOLTAGE INPUT for VREFB5. SSTL is a kind of persudo differential IO standard, a group of SSTL io must have a common reference voltage. You must connect it to a 0.9V voltage source for you are using the VREFB5 group(some of your DQ, DQS, ADDR... are SSTL IOs in this group).

Anothor thing I found:

--- Quote Start ---

set_location_assignment PIN_J16 -to mem_clk[0]

set_location_assignment PIN_K16 -to mem_clk_n[0]

--- Quote End ---

while in 3C10's pin-outs file they are:

DIFFIO_R7n

DIFFIO_R8n

not a differential pair.

I think you shoud place them in a same differential pair.