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Altera_Forum's avatar
Altera_Forum
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15 years ago

DDR2 mem_clk error

Hi there!

I have designed and manufactured a board with a Stratix III chip (E260) and a DDR2 memory chip. I have connected the memory clock (mem_clk of the FPGA controller module) to pins P8/P9 of the FPGA, which are a PLL_clkout differential output pair.

During fitting, I'm a getting the next error: "Differential input mem_clk[0] is assigned to location P9. However, the pin location does not support differential input.". As I understand, the port is defined as INOUT for an internal phase calibration of the clock, although externally, from a top-level point of view, this pin is an output pin. According to this, a problem shouldn't arise from the selection of I/Os which are only available as an output differential pair.

Is there a workaround for this problem, or am I doomed ? :)

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You probably will have to do a re-spin of the board.

    The Alt-MemPHY reads the clock back into a 'mimic' path to check the actual delays while operating, and uses this info to phase-shift the PLL to obtain optimal setup and hold margins.

    I'm not sure whether you can enable the "Use PLL Outputs for Memory Clocks" option in the ddr controller MegaWizard.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks for the response.

    I understand that the FPGA internally reads back the output, but the question is whether the differential signal is being read (and maybe in that case the FPGA pin shouldbe bidirectional) or the internal single ended signal is being read (and in this case, the pin itself shouldn't have to be bidirectional). If it is the latter, I assume that there is a workaround for the error.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The idea is to read back from the pin to correctly mimic the input delays suffered by the returned DQS signals. Reading back the internal signal feeding the IO buffer yields a very short delay only, and which is not easily matched with the real delay of the DQS input buffers.

    Like I mentioned there used to be an option to drive the memory clocks with PLL-output pins, but I can't enable that for my Cyclone IV HPC II project. Perhaps it needs another 'feedback' signal then?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    I'm not sure whether you can enable the "Use PLL Outputs for Memory Clocks" option in the ddr controller MegaWizard.

    --- Quote End ---

    I can't enable it. How come I couldn't enable it? :cry:
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi josyb,

    Could you tell me what do you mean by feedback signal?

    OH, ok. In Stratix you can use DDR2 Controller instead of DDR2 High Performance with ALTMEMPHY.