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Altera_Forum
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15 years ago

DDR2 mem_clk error

Hi there! I have designed and manufactured a board with a Stratix III chip (E260) and a DDR2 memory chip. I have connected the memory clock (mem_clk of the FPGA controller module) to pins P8/P9 of...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks for the response.

I understand that the FPGA internally reads back the output, but the question is whether the differential signal is being read (and maybe in that case the FPGA pin shouldbe bidirectional) or the internal single ended signal is being read (and in this case, the pin itself shouldn't have to be bidirectional). If it is the latter, I assume that there is a workaround for the error.