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Honored ContributorDDR2 HPCII v11.0 problem, thanks for help !
everything seems well, however, local_init_done is always low, what's wrong?
I tried both the full calibration and "skip the calibration", it doesn't change anything, the local_init_done is always low ! PS. I believe the PCB board is good. PS. I tried to use debug toolkit to check the internal states, however, when I downloaded altera.com/technology/memory/dram/altmemphy/debug/debug-toolkit.zip and un-packed it, there is a DEBUG GUI README.txt, which says: This is the Altera ALTMEMPHY Debug GUI. It is an application to view the internal state of the calibration sequencer that initialises the DDR3 ALTMEMPHY Megafunction. But mine memory is DDR2 ! PS. ctl_cal_fail is high and ctl_cal_success is low, what's wrong with the calibration? PS. the memory is sumsung K4T51163QI18 Replies
Altera_Forumcheck if You've connected reset pins properly. Probably You've missed reset and reset_n pins.
- Altera_Forum
Thanks ! There are "global_reset_n" and "soft_reset_n" in the module of DDR2 controller, is there any specification on the duration length of these two "reset_n" ?
- Altera_Forum
Can anybody please answer this? I am having teh same problem.
Is there any specification for the global and soft reser I have connected global to 2ms low pulse, and soft is always high Calibration does not pass for me either - Altera_Forum--- Quote Start --- Can anybody please answer this? I am having teh same problem. Is there any specification for the global and soft reser I have connected global to 2ms low pulse, and soft is always high Calibration does not pass for me either --- Quote End --- Did you check your schematic? Is the memory connected properly? The design synthesizes and passes timing fine?
- Altera_Forum
Yes. I stole the schematics from an earlier working design with Cyclone II/DDR2. All timing passed.
I am using ALTMEMPHY, Cyclone IV and DIMM-240 1G (unbuffered) Calibration does not pass. Also, I can not find the debug_toolkit for external memory testing. Looks like Altera has removed it. Can you please attach it here, if you have it - Altera_Forum
And does it start calibration at all? Did you check your termination and reference voltages? Did you do length matching on the tracks?
- Altera_Forum
Yes I can see activity on DQ/DQS at the startup on oscilloscope, so it does do something.. but fails (local_init_done does not go high)
Yes length matching was done as per DDR2 requirements (~3.5"). Clocks are routed differentially Could it be reset? I am just trying double registering asynchronous. Can you please look at attached schematics. -- I used phy_clk (125Mhz) as my application clock to read/write from ALTMEMPHY. Is this OK? - Altera_Forum
All slacks are positive
Info: Address Command (Fast 1200mV 0C Model) | 4.831 1.662 Info: DQS vs CK (Fast 1200mV 0C Model) | 1.658 1.735 Info: Mimic (Fast 1200mV 0C Model) | 3.017 Info: Phy (Fast 1200mV 0C Model) | 3.017 0.145 Info: Phy Reset (Fast 1200mV 0C Model) | 5.174 0.488 Info: Read Capture (Fast 1200mV 0C Model) | 0.807 0.812 Info: Write (Fast 1200mV 0C Model) | 0.796 1.077 - Altera_Forum
Please see attached. This is Altera example driver with ALTMEMPHY for DDR2 memory
Even with "Skip Calibration" it never ends. It ran all night and only reached 12ms. Look at the result. It only wrote 0x00 and 0xFF in the begining, and then DQ and DQS were inactive for the rest. Test Complete never went high. What is it waiting for? Does this give anybody any clue? I must be doing something very basic wrong - Altera_Forum
Did you regenerate qsys system after changing settings to no calibration?
Are you setting all resets correctly?
