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Altera_Forum
Honored Contributor
10 years agoYes I can see activity on DQ/DQS at the startup on oscilloscope, so it does do something.. but fails (local_init_done does not go high)
Yes length matching was done as per DDR2 requirements (~3.5"). Clocks are routed differentially Could it be reset? I am just trying double registering asynchronous. Can you please look at attached schematics. -- I used phy_clk (125Mhz) as my application clock to read/write from ALTMEMPHY. Is this OK?