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RYuen
New Contributor
New ContributorData Result affected by using signalTap and In-system memory content editor after synthesis in Quartus
Hi everyone I am designing a DSP for a FFT in Quartus15.1 Prime SE and using both signalTap and In-system memory content editor to debug. In my design , the FFT result is stored in a RAM, therefore...
RichardT_altera
Super Contributor
Super ContributorHi,
Have you tried to simulate your design and check whether the simulation meet your expectation?
Please refer to this document on simulating the IP.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_fft.pdf
