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Altera_Forum's avatar
Altera_Forum
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13 years ago

Cyclone V SE SoC FPGA ARM HPS - also with Nios2 buried in FPGA?

Hello,

I have a design on a cyclone, using nios2 with custom logic, custom instructions and quite a bit of assembly code routines, along with C,C++.

If I make the jump to an SoC FPGA, can I continue to have a nios2 operating in the FPGA fabric? Will the development tools allow me to work with the ARM and the Nios2 ?

I would like this solution to allow me to partition the processing and continue to bias the existing hard-real-time stuff onto the FPGA+Nios2.

Some of the non-real-time stuff may migrate onto the ARM, which I expect would eventually do some heavy lifting but initially it would mostly operate standard OS things such as peripherals. I'd probably be drawn to introduce Linux or some OS - for device driver and modern network support. Up to now I have avoided needing an OS.

Any and all comment welcome!

Thanks!

Lefty

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Short answer is yes, what you are looking to do will be possible and I suspect will be a very common setup as well. Treat the SoC device like a regular FPGA that happens to have an embedded SoC block (called the HPS) in the same die with memory mapped connections between the FPGA and HPS. You also have the right idea when it comes to dividing the realtime and non-realtime code amungst the two processor types.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Short answer is yes, what you are looking to do will be possible and I suspect will be a very common setup as well.

    --- Quote End ---

    Thanks, my other concern is availability of silicon. Is there a launch date?

    Perhaps If I am stuck I can partition multiple Nios2 cores onto a regular Cyclone FPGA part? Do the existing NIos2 tools support that configuration?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    For the date, contact your sales rep.

    You could get started on the soft logic side and work your way up to the HPS block. Using Nios II in a SoC device is no different than a standard FPGA. In fact Nios II has no concept of a SoC vs a non-SoC FPGA so if you are an existing Nios II user you won't notice anything different to what you are already accustom to doing.