Cyclone V SE SoC FPGA ARM HPS - also with Nios2 buried in FPGA?

Short answer is yes, what you are looking to do will be possible and I suspect will be a very common setup as well. Treat the SoC device like a regular FPGA that happens to have an embedded SoC block (called the HPS) in the same die with memory mapped connections between the FPGA and HPS. You also have the right idea when it comes to dividing the realtime and non-realtime code amungst the two processor types.