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New Contributor

2 years ago

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Cyclone-V RAM Block

Hi, I am working on existing FPGA project. In the project, RTL instantiates the ASIC memory models. Along with the project there are qip files for memories. My question is how the ASIC memory models...

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ShengN_altera
2 years ago
Hi,

Check these two links https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/reference/glossary/def_qip_file.htm and https://www.intel.com/content/www/us/en/docs/programmable/683609/23-4/files-generated-for-systems.html to understand the functions of the .qip file. Can double-click the .qip file to check all the respective paths included.

Thanks,
Best Regards,
Sheng

ShengN_altera

Super Contributor

2 years ago

Hi,

Check these two links https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/reference/glossary/def_qip_file.htm and https://www.intel.com/content/www/us/en/docs/programmable/683609/23-4/files-generated-for-systems.html to understand the functions of the .qip file. Can double-click the .qip file to check all the respective paths included.

Thanks,

Best Regards,

Sheng

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Cyclone-V RAM Block

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