Cyclone V GX and alt_iobuff_diff

Hello,

You should not use the primitive ALTIO_BUFF_DIFF directly as this is not the correct approach.

You should use Differential 1.2V HSUL for DQS signals.

Cyclone V devices are typically paired with the Intel UniPHY IP to implement memory interfaces, including LPDDR2.

The UniPHY controller automatically handles differential DQS signals and takes care of timing calibration and bidirectional operations.

If you’re not already using the UniPHY IP, consider generating the LPDDR2 interface using the DDR2/DDR3 SDRAM Controller with UniPHY IP in Quartus.

regards,

Farabi