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Altera_Forum's avatar
Altera_Forum
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17 years ago

Cyclone III SOPC and Intel Flash pin problem

I seem to be doing something pretty wrong when it comes to setting up my system with my Cyclone III starter kit. I am building an SOPC builder system, and use the "CFI Flash" component, and configure it with the "Intel 256P30" device. This seems straight forward enough.

When i go to the pin assignment section though, i have Address[24..1], data[15..0], read_n, select_n, and write_n outputs of my block in my top level schematic.

My problem is that the actual device has these pins:

we_n, ce_n, oe_n, reset_n, adv_n, clk, and wait signals.

The documentation of the CFI block assumes just 3 signals, but nothing about handling those other pins. The 103 page P30 Family flash document contains loads of different configurations for the flash device, synchronous, asynchronous, but I don't know how the CFI block is actually interfacing to the device.

I am sure there is something completely obvious I am missing, I would be very appreciative if someone could point it out to me.

Thanks

-Art

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The said synchronous flash interface pins exist as dedicated AP pins in Cyclone III, as the Configuration Handbook clarifies. So there shouldn't be a problem where to connect the pins. I don't know, if they are also supported by other flash related IP, apparently not in PFL Megafunction. This means, that the PFL access to Intel flash is asynchronous only.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    what are "dedicated AP pins" ?

    I have searched the Cyclone III Starter Kit : User Guide, Reference Manual, and Quick Start Guide. Also the Cyclone 3 Device Manual, and have seen no reference to an "AP pin", can you explain what that is?

    I can connect write_n to we_n, and read_n to oe_n, and select_n to ce_n.

    It looks like i want to just connect clk to 0, and adv_n to 0, and float the wait signal? From the picture. Does this sound right?

    -Art
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I assumed, that the flash is used for FPGA configuration, then the configuration scheme is active parallel (AP) and the flash has to use the dedicated pins. But I see that you didn't say a word about used configuration scheme.

    If you don't use flash for configurations, simply follow the P30 handbook:.

    --- Quote Start ---

    If only asynchronous reads are to be performed, CLK should be tied to a valid VIH level, WAIT signal can be floated and ADV# must be tied to ground.

    --- Quote End ---