Cyclone III SOPC and Intel Flash pin problem

I assumed, that the flash is used for FPGA configuration, then the configuration scheme is active parallel (AP) and the flash has to use the dedicated pins. But I see that you didn't say a word about used configuration scheme.

If you don't use flash for configurations, simply follow the P30 handbook:.

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If only asynchronous reads are to be performed, CLK should be tied to a valid VIH level, WAIT signal can be floated and ADV# must be tied to ground.

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