Cyclone 10 SERDES Receiver Timing Constraints

Hi,

Sorry for delay reply,

Check this https://www.intel.com/content/www/us/en/docs/programmable/683520/22-1-20-0-1/timing.html:

Use the Intel® Quartus® Prime software from version 14.0.a10 onwards to generate the required timing constraint to perform proper timing analysis of the LVDS SERDES IP core in Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.

And this https://www.intel.com/content/www/us/en/docs/programmable/683520/22-1-20-0-1/i-o-timing-analysis.html:

In non-DPA mode, use RSKM, TCCS, and sampling window (SW) specifications for high-speed source-synchronous differential signals in the receiver data path. If there is additional board channel-to-channel skew, consider the total receiver channel-to-channel skew (RCCS) instead of TCCS where .

Now you just need to set the RCCS, then it'll be auto implemented into auto-generated .sdc.

RCCS = (Clock trace delay) - (Data trace delay) + margin

Skew(ps) = (Trace length different in mm) * (propagation delay per mm, typically 5ps/mm for FR4)

For example if your pcb analysis shows that the clock trace is 2mm longer than the data trace:

Skew = 2mm * 5ps/mm = 10ps

Add margin = (e.g. 20ps) = 30ps

Set RCCS to 30ps

Thanks,

Regards,

Sheng