Custom Verilog module I/O missing :(

Hello!

I have a working design in Quartus II 9.1 that targets a Cyclone III. I want to add a custom component that I have written in Verilog. I have managed to add the component using SOPC Builder (which is the only way I have found to do it). Problem is that the component has no ports. It is just a brick with nothing to connect wires to.

Below is the Verilog code:

module Pulse2LogicLevel (RisingEdge, FallingEdge, LogicLevel);

// I/O Ports:

output LogicLevel;

input RisingEdge, FallingEdge;

// Internal Registers:

reg tmp, prevLL, prevRE, prevFE;

always @(RisingEdge or FallingEdge)

begin

tmp = ((RisingEdge == 1'b1) && (prevRE == 1'b0)) || prevLL;

prevLL = !((FallingEdge == 1'b1) && (prevFE == 1'b0)) && tmp;

prevRE = RisingEdge;

prevFE = FallingEdge;

end

assign LogicLevel = prevLL;

endmodule // Pulse2LogicLevel

As you can see, I have specified two input ports and one output port. I expected to see these as the I/O ports of the component I created in Quartus. Below is the procedure I used to add the component.

1) Double-click in Quartus II canvas to bring up the symbol insert page

2) Click "MegaWizard Plug-In Manager..." button

3) Select "Create a new custom megafunction variation" button on pop-up, then click "next"

4) Select "Altera SOPC Builder" megafunction, select "Verilog HDL" radio button, and provide name for output file "foo" in my project directory, then click "next".

5) In SOPC Builder, double-click "new component"

6) On "HDL Files" tab click "add..."

7) Browse to and open my source Verilog file, in this case "pulse2logiclevel.v".

8) On "Signals" tab I see all 3 of my I/O signals: RisingEdge, FallingEdge, and LogicLevel. By default they are set to the avalon_slave_0 interface type. These are not avalon signals, they are simply signals that I want to connect externally at the top level in Quartus. Therefore I CHANGE the interface type to "conduit_end" for all of them. I change the "signal type" for all of them to "export". In theory (according to documentation anyway) this should make these appear as ports on the SOPC component that will ultimately get instantiated in Quartus at the top level.

9) On the "Interfaces" tab I click "Remove interfaces with no signals". This eliminates all warnings and errors. The block diagram on this page shows my 3 signals marked as "export".

10) I click "finish". The component editor closes and a new component Pulse2LogicLevel appears in my "Library" on the left side of SOPC Builder.

11) Double-click Pulse2LogicLevel to add it to my system.

12) Click "generate" to generate the system. It generates successfully with no errors or warnings.

13) Save and Exit SOPC Builder, bringing me back to the symbol insertion popup.

14) The "foo" symbol is displayed in the symbol insertion window. It has no ports.

15) I click "ok" and place an instance of the component at the top level of my Quartus design. As expected, the instance has no ports.

I am either doing something wrong or am leaving out a step or 2. Does anyone see what I am doing wrong?

Thanks for any help you can offer!

LH