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matferronato's avatar
matferronato
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2 years ago
Solved

Current module quartus_fit was unexpectedly terminated by signal 9

Hello, I found some other topics discussing this issue, but couldn't find an answer to my problem. Currently, my design consumes most of the a available logic in the FPGA. When I try to run the fi...
Hdl
matferronato's avatar
matferronato
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2 years ago

Hi sstrell.

Indeed an Agilex device. It seems that the computers resources are being exhausted.

Does intel provide any info on the minimum specs required to correctly synthesize a design to a target architecture?

I can understand why the lack of memory had me consistently fail place and route, what I don't get is why sometimes it worked.

Does anyone know a possible workaround? (besides upgrade memory/cpu)

Thanks for your help