Crossing Clock Domain Problems | Timing Analyser ignores set_max_skew assignment

Hello everyone,

I have a problem with quartus 20.1 while trying to cross a clock domain. I have followed the Intel video regarding the crossing https://www.youtube.com/watch?v=RTcZOl2e8PI and the Intel Help https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/tools/2017/how-do-i-constrain-my-clock-domain-crossing-.html .

I also have attached the code for the synchroniser at the bottom. However Timing Analyser always reports that it ignores the set_max_skew assignments with the following message:

No path is found satisfying assignment "set_max_skew -from [get_registers {neuralNetwork|InputSync|clk1_Buffer[*][*]}] -to [get_registers {neuralNetwork|InputSync|clk2_Buffer[0][*][*]}] 2.693 ". This assignment will be ignored.

It does not matter if i use from_clock or from with the registers. I get the same error.

However I do not get any warning during analysis as I would if I would have a wrong path in there (had typos in there and got the warning).

The problem is that I can not use the max_skew report and thus see if the timings are actually held. Does anyone have any idea?

Best regards
Christian

Edit: I have just checked in the TA. I can find the registers when setting up new assignments. I also tried setting just the individual register connections, which I can definitively find the Technology Map Viewer. It also gets ignored.

Edit 2: I have now looked through the output for the timing analyser during compilation. There it says it detects all of the synchronizer chains, calculates a MTBF, settling time, etc.
Afterwards I went ahead and tested the design on the FPGA and all output look good. I really do not understand why TA is not able to create the report. Any ideas?

SDC constrains:

**************************************************************
# Create Clock
#**************************************************************
create_clock -name {input_clk} -period 13.468 -waveform { 0.000 6.734 } [get_ports {clk}]

#**************************************************************
# Create Generated Clock
#**************************************************************

create_generated_clock -name output_clk -source [get_ports {clk}] -master_clock input_clk -add [get_ports {clk_o}]
create_generated_clock -name {pllBaseClock} -source [get_pins {neuralNetwork|PLL|nnfpga_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 16 -divide_by 2 -master_clock {input_clk} [get_pins {neuralNetwork|PLL|nnfpga_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] 
create_generated_clock -name {neuralNetworkClock} -source [get_pins {neuralNetwork|PLL|nnfpga_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 2 -master_clock {pllBaseClock} [get_pins {neuralNetwork|PLL|nnfpga_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]  

#**************************************************************
# Set Clock Groups
#**************************************************************

set_clock_groups -asynchronous -group [get_clocks {neuralNetworkClock}] -group [get_clocks {input_clk}] 


#**************************************************************
# Set Net Delay
#**************************************************************

set_net_delay -max 2.693 -from [get_pins {neuralNetwork|InputSync|clk1_Buffer[*][*]|q}]
set_net_delay -max 2.693 -from [get_pins {neuralNetwork|OutputSync|clk1_Buffer[*][*]|q}]


#**************************************************************
# Set Max Skew
#**************************************************************

set_max_skew -from [get_registers {neuralNetwork|InputSync|clk1_Buffer[*][*]}] -to [get_registers {neuralNetwork|InputSync|clk2_Buffer[0][*][*]}] 2.693
set_max_skew -from [get_registers {neuralNetwork|OutputSync|clk1_Buffer[*][*]}] -to [get_registers {neuralNetwork|OutputSync|clk2_Buffer[0][*][*]}] 2.693

synchronizer:

-- Synchorniser for array of std_logic_vector of variable size
-- Requires VHDL 2008 support! 
--
-- (c) Christian Woznik

library IEEE;
use ieee.std_logic_1164.all;

USE ieee.math_real.log2;
USE ieee.math_real.ceil;

library work;
use work.types.all;

entity synchroniserArrayStdLogicVector is
	generic (arraySize 		: integer;
				stages			: integer;
				inputdataWidth : integer);
				
	port (clk1        : in 	std_logic;
			clk2 			: in 	std_logic; 			
			
			dataIn		: in variableSizeLogicVectorArray (0 to (arraySize) -1)(inputdataWidth-1 downto 0);
			
			dataOut 		: out variableSizeLogicVectorArray (0 to (arraySize) -1)(inputdataWidth-1 downto 0));
			
end synchroniserArrayStdLogicVector ;


architecture behave of synchroniserArrayStdLogicVector is	
	signal clk1_Buffer : variableSizeLogicVectorArray (0 to (arraySize) -1)(inputdataWidth-1 downto 0);
	
	type t_BufferArray is array (0 to stages-1) of variableSizeLogicVectorArray(0 to (arraySize) -1)(inputdataWidth-1 downto 0);
	signal clk2_Buffer : t_BufferArray;
begin
	process(clk1)
	begin	
		if rising_edge(clk1) then
			clk1_Buffer <= dataIn;
		end if;
	end process;
	
	process(clk2)
		variable i : integer;
	begin
		if rising_edge(clk2) then
			clk2_Buffer(0) <= clk1_Buffer;
			for i in 0 to stages-2 loop
				clk2_Buffer(i+1) <= clk2_Buffer(i);
			end loop;
		end if;
	end process;
	
	dataOut <= clk2_Buffer(stages-1);
end behave;