Crossing Clock Domain Problems | Timing Analyser ignores set_max_skew assignment

The answer is easy: Quartus has a bug since at least Quartus 16.1, which means you cannot use "set_max_skew" to constrain "Clock Domain Crossing" paths (CDCs); which is unfortunate, because this is the correct constraint for these kind of paths.

Note that even if you would be able to use "set_max_skew" it wouldn't help, because the fitter ignores these constraints.

Additionally you can only use "set_net_delay" for CDC paths, which do not contain ANY combinational logic in between; so you can only use "set_net_delay" for pure register to register paths.

The only way to get reliable CDC logic is to put it into an own entity and then use "logic lock" regions to make sure the fitter puts all the registers as close together as possible.

To get some notion about timings for CDC logic, you then need an extra "SDC" file, where you remove all "set_false_path" and "set_clock_group" constraints, because then the timing analyzer will be at least able to give you numbers for the "set_max_skew" constraints.

Welcome to the world of unreliable tools and "community" support, which does not even understand what you are talking about.