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Christian_Woznik's avatar
Christian_Woznik
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4 years ago

Crossing Clock Domain Problems | Timing Analyser ignores set_max_skew assignment

Hello everyone, I have a problem with quartus 20.1 while trying to cross a clock domain. I have followed the Intel video regarding the crossing https://www.youtube.com/watch?v=RTcZOl2e8PI and the ...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
4 years ago

Christian,


What version of Quartus are you using? If you are using Pro, there is feature like DA DRC for CDC and CDC Viewer report in Timing Analyzer which will tell you there is CDC still occur in your design easily.


Since you mentioned during compilation the PnR works and the output is correct, no meta. furthermore no hardware failure during testing and error during compilation, this could be a bug as well for TA. Is it possible to attach you qar here to reproduce the issue.