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Altera_Forum's avatar
Altera_Forum
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13 years ago

Creating Verilog code from RTL ?

Hi,

Using QuartusII, I have built and compiled my design using the Block (schematic) editor, and now wish to simulate it in ModelSim. The compilation generates a .vo file which is a Verilog representation of the final implementation (on a MaxII device in my case), which can be read by ModelSim.

This works OK, but does not allow me access to any internal nets, because they whole structure is remapped to suit the target device. The internal nets I want to monitor are all in there somewhere, but it is virtually impossible to work out what's what.

A workaround is to connect the internal nets I want to see to output pins, but this seems very clunky, and means the final design is not quite what I will be simulating -- scope for mistakes.

The compilation also produces an RTL representation, and it seems to me that a Verilog version of this RTL would be much more suitable for simulation, and would allow easy identification of internal nets. Is there any way of generating Verilog from the RTL, or any other way of generating a simpler Verilog version than the standard .vo file ?

Thanks, Ken.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    you should have the option of creating Verilog directly from the schematic file-> create/update -> create HDL design from current file.

    This is just an RTL file. nets should preserve their names as per the schematic. Unnamed nets will be given generated (and annoying) names.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hello,

    Thanks for reply to my question. This works just as you say, which is a good start. Now have some problems in ModelSim getting it to find the instantiations, but that will be a question for a different forum, and I havn't exhausted all possibilities yet.

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Just an update on where I've got to.

    The key file for simulating verilog created from HDL is:

    C:\altera\12.0sp2\quartus\eda\sim_lib\220model.v

    This contains the behavioural code for all megafunctions (lpm).

    When this is compiled, plus all higher level blocks in the design, the

    simulation runs fine, and as would be expected it is much faster than

    running the .vo file which corresponds to the detailed chip level implementation. Also allows access to internal nets, as long as they are named in the Quartus schematic.

    So problem solved and back on track ('til next hurdle!).

    Many thanks, Ken.