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Altera_Forum's avatar
Altera_Forum
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13 years ago

Creating Verilog code from RTL ?

Hi, Using QuartusII, I have built and compiled my design using the Block (schematic) editor, and now wish to simulate it in ModelSim. The compilation generates a .vo file which is a Verilog repre...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hello,

Thanks for reply to my question. This works just as you say, which is a good start. Now have some problems in ModelSim getting it to find the instantiations, but that will be a question for a different forum, and I havn't exhausted all possibilities yet.

Thanks.