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Altera_Forum's avatar
Altera_Forum
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13 years ago

Creating Verilog code from RTL ?

Hi, Using QuartusII, I have built and compiled my design using the Block (schematic) editor, and now wish to simulate it in ModelSim. The compilation generates a .vo file which is a Verilog repre...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

you should have the option of creating Verilog directly from the schematic file-> create/update -> create HDL design from current file.

This is just an RTL file. nets should preserve their names as per the schematic. Unnamed nets will be given generated (and annoying) names.