Creating Verilog code from RTL ?

Just an update on where I've got to.

The key file for simulating verilog created from HDL is:

C:\altera\12.0sp2\quartus\eda\sim_lib\220model.v

This contains the behavioural code for all megafunctions (lpm).

When this is compiled, plus all higher level blocks in the design, the

simulation runs fine, and as would be expected it is much faster than

running the .vo file which corresponds to the detailed chip level implementation. Also allows access to internal nets, as long as they are named in the Quartus schematic.

So problem solved and back on track ('til next hurdle!).

Many thanks, Ken.