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Altera_Forum's avatar
Altera_Forum
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15 years ago

Creating RPM for altera devices

Is there any equivalent of RPM (Relatively Placed Module) in Altera. Basically to meet timing I want to place to a set of flip flops near the MLABs. Since there are many such instantiations of these set of flops and MLABs I can not give area constraint on all these flops and MLABs.

In xilinx we can group these set of FLOPS and MLABs (or distributed RAMs) together and guide the tool to place these as a group. So wherever tool sees this group it places them nearby. This is called creating RPM (Relatively Placed Module). Can we do something similar in Altera. I am currently using a Stratix4 device.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You could do this with floating Logic Lock Regions, but the Fitter does a much better job in Quartus II, so you will likely find that this is not necessary to meet timing. If you find that this is not the case for your design, you may be better off trying to overconstrain these paths with set_max_delay timing constraints.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Not exactly. Incremental compilation can be used to lock down placement(and routing if you want), but can't be stamped out onto different locations. A design can be back-annotated, whereby the logic will get specific X/Y locations, which could be modified into relative placements, but it is not trivial. Both of these will lock the logic down to exact locations.

    If you want the whole block to "float", you can do a floating LogicLock region, but the exact locations inside won't be locked.

    To be honest, floating LLRs are not a great thing for placement(and they're less restrictive than RPMs, so RPMs would only be worse). It is difficult for placers to move large groups of logic, since they dislocate so much other logic and hence any movements are very distruptive. It's like trying to fill a jar with rocks, but only having large stones instead of small pebbles.

    Finally, I would make sure you need it. It's a nice comfort factor, but the fitter does a very good job of placing things. And when it doesn't, it's usually because other factors affect that, which wouldn't be resolved by an RPM. I used to do some of those(back in the XC4000 days), but really haven't found a need with Altera devices.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I will try logic lock regions but what i understand from your replies, I believe that these things are usually not required in Altera devices.

    I have the following issue. I am targetting a design in Stratix4gx-230 device which is running at 311 Mhz. The utilization is around 90%. Now I am able to achieve the timing almost in complete design except the places where I have used MLABs as dsitributed RAM (dual port). My complete design is working at positive edge of the clock. But it seems that there is some path inside the MLAB where the data goes from negative edge to positive edge. Somehow I am not able to meet timing on most of those paths. I am not very sure whether using logic lock regions will resolve this problem or not!!

    Do you have any suggestion how can I make it work?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I assume these paths meet timing when the design isn't full? LogicLock should probably work, but make it as small as possible so the registers are forced right next to the MLAB. This path has a ~3ns setup requirement because of the fall -> rise transfer.

    Another thought might be to make the logic before the register negative edge triggered also. This will push back the rise->fall requirement before the memory, which might be more do-able(if that path has much logic, it will only make things worse).