Creating RPM for altera devices

I assume these paths meet timing when the design isn't full? LogicLock should probably work, but make it as small as possible so the registers are forced right next to the MLAB. This path has a ~3ns setup requirement because of the fall -> rise transfer.

Another thought might be to make the logic before the register negative edge triggered also. This will push back the rise->fall requirement before the memory, which might be more do-able(if that path has much logic, it will only make things worse).