Honored Contributor
Honored ContributorI will try logic lock regions but what i understand from your replies, I believe that these things are usually not required in Altera devices.
I have the following issue. I am targetting a design in Stratix4gx-230 device which is running at 311 Mhz. The utilization is around 90%. Now I am able to achieve the timing almost in complete design except the places where I have used MLABs as dsitributed RAM (dual port). My complete design is working at positive edge of the clock. But it seems that there is some path inside the MLAB where the data goes from negative edge to positive edge. Somehow I am not able to meet timing on most of those paths. I am not very sure whether using logic lock regions will resolve this problem or not!! Do you have any suggestion how can I make it work?
