Creating clock sources in SOPC Builder

You should just define your clock in SOPC builder and an input port will be created on the SOPC component. Connect that port to either a pll or a FPGA input pin.

What do you exactly mean by "creating a clock" in verilog? The only good clock you can have in an FPGA is from an external source, or a pll driven by an external source. Creating an oscillator with logic cells will be at best very unreliable, and if you are using delays in the verilog code it won't be synthesizable.

Thanks for the response Daixiwen

The clock source is generated from a PLL instantiated from within an existing verilog module which I am trying to port to the Avalon protocol. (I'm trying to bring a fairly complex project into SOPC Builder by creating Avalon MM ports for each of the modules and re-writing code where necessary). Is it possible to instantiate a PLL from a custom component within SOPC Builder? or do I need to restructure the code so that the PLL is instantiated from within SOPC Builder or the top level Quartus system?

Ref you're other comment, I connected the clock output from the SOPC Builder to an output pin so I could view it on a scope - that's when I get the error message in the previous post.

My other thought was that simulating the hardware in SOPC Builder might resolve the issue - I'm currently working through a Modelsim licensing issue.

Any thoughts on any of the above would be gratefully received

I don't see why it wouldn't be possible, but it's true that the most common way to do that is either to have the pll outside of the SOPC project, or use the ready made pll component inside SOPC builder.

I just had a look at the component creator documentation and the avalon spec, and couldn't find any clock interface property or tcl command that would define the frequency of a clock lource so I don't know how they do that. Maybe instantiating a pll component in a SOPC builder project and have a look at the generated files could shed some light on that, but it doesn't seem to be documented.

Thanks Daixiwen,

I think I'll restructure the existing modules so that the PLLs are instantiated from SOPC builder and then the clock outputs are passed to the relevant modules. We're looking to create a project structure that will allow multiple users to easily add / replace modules in the system using Avalon MM so I think the more visible the clocking structure in SOPC Builder, the better.

Thanks again

Try this:

set_interface_property <your_output_clock_interface> clockRate <clock_rate_in_Hz>

you might need to add this as well:

set_interface_property <your_output_clock_interface> clockRateKnown 1

Note: I copied these out of a component available in Qsys and have no clue if this will work in SOPC Builder

Actually, we've taken the decision to use PLLs in the top level Quartus system to generate clocks and then import them into SOPC Builder. This means we have to re-write some of our existing modules but it will make it easier for future developers to integrate new modules into the system.

Thanks anyway,

John

--- Quote Start ---

Try this:

set_interface_property <your_output_clock_interface> clockRate <clock_rate_in_Hz>

set_interface_property <your_output_clock_interface> clockRateKnown 1

--- Quote End ---

I tried this in SOPC Builder 9.1 and it worked fine, solved my problem. Thanks.