Honored ContributorI have .qsys files of a project for which I want to create BDF files in Quartus prime. I hope it's possible to create BDF file automatically without going for manual connections between blocks (created using BSF files). Please do reply if anyone knows about it.
Honored ContributorOver the years I don't recall such functionality being present. Quartus can create the symbol files for you but it will not generate an entire schematic complete with connectivity from RTL source files as far as I know.
Honored ContributorHonored ContributorJust hoping bdf files can give more clear and detailed picture of the project to viewer than RTL schematic if I can generate BDF files automatically.
Honored ContributorI am afraid that Quartus can not do that automatically you have to create it manually. From personal experience I can say that working with .bdf schematic files at first looks quite attractive. But as soon as your project grows bigger and more complex it becomes nightmare to make and track changes.
Honored ContributorIn general usually when software generates source files they are not very readable. So generating a bdf from Verilog/VHLD sources would probably be very difficult to understand. If you have ever looked at the RTL Quartus generates from a .bdf source file you'll see what I mean :)
Like vlrean said, schematics do not scale to large projects well. Also keep in mind that you'll probably eventually want to simulate your logic so you are better off with industry standard RTL like Verilog, System Verilog, or VHLD that most/all simulators can interpret.
