Creating BDF file in Quartus prime

In general usually when software generates source files they are not very readable. So generating a bdf from Verilog/VHLD sources would probably be very difficult to understand. If you have ever looked at the RTL Quartus generates from a .bdf source file you'll see what I mean :)

Like vlrean said, schematics do not scale to large projects well. Also keep in mind that you'll probably eventually want to simulate your logic so you are better off with industry standard RTL like Verilog, System Verilog, or VHLD that most/all simulators can interpret.