create_clock .sdc syntax

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Hi,

I am trying to specify a period constraint to input_clk[1] port of a PLL.

Every example I can find shows:

create_clock -period 10.000 -name clk [get_ports {clk}]

The issue is that I have two PLLs which have the same port names.. so how do I modify the [get_ports{clk}] parameter to specify a specific PLL port?

I've tried including a specific instance name but TA barfed... Any ideas?

thx

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Hi,

have look to the small attached project. Maybe it will answer your question.

Kind regards

GPK