create_clock .sdc syntax

From what I understand, ports are a top-level entity concept from the timing analyzer's perspective. So, when you refer to [get_ports {clk}], the timing analyzer is looking for an I/O port on your top-level entity called clk. Ports of internal instances, like your PLL, are pins from the timing analyzer's perspective. In order to create a clock on your PLL input source, you can either create the clock on the T/L entity port using the syntax you described or you can create the clock on the PLL instance port/pin using something like [get pins {<hierarchical_path_to_pll>/<pll_clk_pin>}].