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Altera_Forum's avatar
Altera_Forum
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9 years ago

Counter, synthesize problems

Hi, I have problems with my counter. Sorry for my poor english https://forum.digilentinc.com/uploads/default_wink.png Register should be reset on the posedge of signal x1 and should be increased on every posedge of CLOCK. I know that register and ENABLE should be changed only in one always process, but I don't know how do that. The error is:

Line 33: Signal register[11] in unit blagam_o_synteze is connected to following multiple drivers:

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    --- Quote Start ---

    I know that register and ENABLE should be changed only in one always process

    --- Quote End ---

    This is true - and true of ALL signals that you wish to implement in hardware. However, in your code you have both "register" and "ENABLE" each appearing in two always blocks.

    Rather than writing it for you, take a look at this simple verilog counter example: 8-bit simple up counter (http://www.asic-world.com/examples/verilog/simple_counter.html).

    --- Quote Start ---

    Register should be reset on the posedge of signal x1

    --- Quote End ---

    A register can only be clocked by one signal. By using the keyword "posedge" in that way you have, you are implying the "ENABLE" and "register" registers should be clocked by "x1". However, in your case you need it to be clocked by "CLOCK". So, you can't do exactly what you're suggesting. However, as in the example I've pointed you at, the counter "out" is reset on a rising edge of "clk" whenever "reset" is HIGH. I'd suggest you want to do the same and reset "register" to zero whenever "x1" is HIGH, but only on a rising edge of "CLOCK".

    Cheers,

    Alex