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I know that register and ENABLE should be changed only in one always process
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This is true - and true of ALL signals that you wish to implement in hardware. However, in your code you have both "register" and "ENABLE" each appearing in two always blocks.
Rather than writing it for you, take a look at this simple verilog counter example:
8-bit simple up counter (
http://www.asic-world.com/examples/verilog/simple_counter.html).
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Register should be reset on the posedge of signal x1
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A register can only be clocked by one signal. By using the keyword "posedge" in that way you have, you are implying the "ENABLE" and "register" registers should be clocked by "x1". However, in your case you need it to be clocked by "CLOCK". So, you can't do exactly what you're suggesting. However, as in the example I've pointed you at, the counter "out" is reset on a rising edge of "clk" whenever "reset" is HIGH. I'd suggest you want to do the same and reset "register" to zero whenever "x1" is HIGH, but only on a rising edge of "CLOCK".
Cheers,
Alex
Honored Contributor
