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Altera_Forum's avatar
Altera_Forum
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10 years ago

Correct constrain (error 332060: "... was determined to be a clock but ...")

Hi,

I have a warning that I want to disappear.

"s_synth_clk was determined to be a clock but was found without an associated clock assignment"

Yes, this is a clock. Does anyone here know how I "correctly" can constrain it (and make the warning disappear)?

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syntclk : process(clk, reset, synth_div, synth_tacho_en)

begin

if (synth_tacho_en = "10") then --ENABLE

if reset = '1' then

s_synth_clk <= '0';

s_synth_cnt <= (others => '0');

elsif (rising_edge(clk)) then

s_synth_cnt <= s_synth_cnt + 1;

if (synth_div(7) = '1') then

s_synth_clk <= s_synth_cnt(7);

elsif (synth_div(6) = '1') then

s_synth_clk <= s_synth_cnt(6);

elsif (synth_div(5) = '1') then

s_synth_clk <= s_synth_cnt(5);

elsif (synth_div(4) = '1') then

s_synth_clk <= s_synth_cnt(4);

elsif (synth_div(3) = '1') then

s_synth_clk <= s_synth_cnt(3);

elsif (synth_div(2) = '1') then

s_synth_clk <= s_synth_cnt(2);

elsif (synth_div(1) = '1') then

s_synth_clk <= s_synth_cnt(1);

else

s_synth_clk <= s_synth_cnt(0);

end if;

end if; --CLK

else --NOT ENABLE

s_synth_cnt <= (others => '0');

s_synth_clk <= '0';

end if;

end process;

synth_clk <= s_synth_clk;

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Generating logic clocks like this is very bad practice in FPGAs. As are asynchronous enables.

    You should generate clock enables instead - this will remove the warning.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    a clock enable would just go high for 1 clock in N cycles, depending on what division you wanted.

    All you need is an edge detector for each counter bit. Then you'll get the same pattern you had before. Did you really want your clock to have a varying duty cycle?