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Honored Contributor
Honored ContributorCorrect constrain (error 332060: "... was determined to be a clock but ...")
Hi, I have a warning that I want to disappear. "s_synth_clk was determined to be a clock but was found without an associated clock assignment" Yes, this is a clock. Does anyone here ...
Altera_ForumHonored Contributor
Honored Contributora clock enable would just go high for 1 clock in N cycles, depending on what division you wanted.
All you need is an edge detector for each counter bit. Then you'll get the same pattern you had before. Did you really want your clock to have a varying duty cycle?
