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Altera_Forum
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11 years ago

Correct constrain (error 332060: "... was determined to be a clock but ...")

Hi, I have a warning that I want to disappear. "s_synth_clk was determined to be a clock but was found without an associated clock assignment" Yes, this is a clock. Does anyone here ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Generating logic clocks like this is very bad practice in FPGAs. As are asynchronous enables.

You should generate clock enables instead - this will remove the warning.