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You can certainly separate the TX & RX paths such that they run from separate clocks. You can also play with the TX timing such that it '
transmits on the rising edge'.
However, I'm not sure about your RX idea - I'm not sure you're explaining it fully. '
receives on the falling edge' - how are you going to ensure your RX data lines up nicely with your falling edge? By all means run your logic from the negative edge of a clock (although that doesn't achieve anything) but you'll still have to detect an edge such that you can sample the RX data at an appropriate point.
If you simply modify '
baud_16x_enable' to '
keep it enabled' your logic will run 16 times faster than it should.
Try your change, simulate it and see if it behaves as you want.
Cheers,
Alex
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I was describing just the approach for the Tx portion as the first step. Incidentally, the state machine had to be slightly tweaked since it was counting 16 clocks before transitioning states, so had to change that as well, but it's working fine.
For the Rx portion, it also looks like its counting 8 clocks before reading the data line, so a similar tweak might work, i.e. no clock counting, just latching the data based on a sync clock instead of the system wishbone clock.
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