Hi all, I am new here. I tell you my problem. I have been now several days trying to figure it out how to control shift registers SIPO 74LS164 with my FPGA. I am doing a clock, displaying hours, minutes and seconds with NIXIE tubes. What I need to do is to send each second, 24 bits, and remain those 24 bits displaying in the NIXIE tubes during the second, till the new second comes and new 24 bits are sent. Maybe this is a stupid question but I don't know how to produce my clock signal and my serial output to control this ICs.I already have a vector of 24 bits and the schematic of how cascading these ICs so that's not the problem. I think you get which my problem is.Please if somebody can help me would be so so great!Thank you very muchRegards

Doube-Post: http://embdev.net/topic/309166

Design a finite state machine. The states may be: s0 - wait for a internal "start" signal goes to '1', that triggers the transmission. If this is true, load register n with 24 ( 24 bits ) and go to state s1. s1- put a data bit on 74LS164 serial in. go to state s2 s2 - rise 74ls164 clock signal. go to state s3 s3 - place '0' on 74ls164 signal. go to state s4 s4 - shift data register, decrement n register. go to state s5. s5 - if n register is 0 you ended your transmission. If no 0, go to state s1. Translate this to vhdl. You could do with fewer states.

Thank you very much for your reply, it helped me a lot on how focus the problem. Now my problem is with the state machine itself. I paste here the code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; entity control_unit2 IS port (clk2: in std_logic; clk: in std_logic; data : in std_logic_vector (23 downto 0); data_out : out std_logic; clk_out : out std_logic); end control_unit2; Architecture Behavioral of control_unit2 is type state_type is (start, load, pulse, rst, shift, check); signal pstate, nstate : state_type := start; signal data_reg : std_logic_vector (23 downto 0); signal data_aux: std_logic ; signal clk_aux: std_logic; signal trigger: std_logic := '0'; BEGIN clocked: PROCESS (clk2,clk) BEGIN if clk2'event and clk2 = '1' then pstate <= nstate; END IF; END PROCESS clocked; states: process(pstate,data,trigger, clk) variable i : integer; begin case pstate is when start => i := 24; data_reg <= data; nstate <= load; when load => data_aux <= data_reg(i); nstate <= pulse; when pulse => clk_aux <= '1'; nstate <= rst; when rst => clk_aux <= '0'; nstate <= shift; when shift => i := i - 1; nstate <= check; when check => if i = 0 then nstate <= waiting; else nstate <= load; end if; end case; end process states; clk_out <= clk_aux; data_out <= data_aux; END Behavioral; The problem is in the state 0. My start signal, following your explanation, is a falling edge of the clock clk. That falling edge tell me when a second starts, i.e. when I must start sending data through the output. When I try to synthesize this I get this error: Error (10822): HDL error at control_unit2.vhd(55): couldn't implement registers for assignments on this clock edge I don't know where is the problem and what should I do to solve it. Can you help me? Thank you again. Regards

The code looks very good. But u have to fix some things: a-u have 2 inputs clocks: clk and clk2. Your design needs no more than 1 clock. b-u separate the register description from the next state logic. I like that, it's very clear. But when u declare pstate and nstate u assign an initial state ( start ). This doesn't work. It only have sense for simulation purposes. Set an initial state in the register description: if( reset = '0' ) then pstate <= start; elsif(clk'event and clk = '1') then pstate <= nstate; end if; c-You have a trigger signal. How do u use it? And where you generate it? d-I don't now where is the line 55, that generates the error. Regards.

Thank you for your reply. Regarding the 2 clocks, one its acting like a clock itself (clk2), but the other one is the 1 Hz signal generated to get the seconds value and synchronized with the DCF77 signal (it's a long wave time signal, which I use for this project). This 1 Hz signal is generated in another block (I'm doing this with blocks in Quartus II). I need that 1 Hz clock to send the datas at the beginning of the second (falling edge of this signal). b. I think I get the point but the problem is that I need, like I said before, to go to the "start" state, each time I get a falling edge on clk (1 Hz signal) and that's the problem I have, I don't know how to do this. c. Sorry for that, it's just something I was trying and then forgot to delete it. d. I pasted you another code sorry, just change in the description of the "start" state and here it is and it's where I get the error: begin case pstate is when start => if clk'event and clk = '0' then -- Falling edge on the 1 Hz clock i := 24; data_reg <= data; nstate <= load; else nstate <= start; end if; What I am trying to do here, is to create a "bucle" in the "start" state, waiting for that falling edge. I hope I make myself clear. Thank you again, very much. Regards

Control shift registers with FPGA | Altera Community

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Altera_Forum

Honored Contributor

12 years ago

Finally! It worked! I didn't use the "hold" state at the end, I didn't see it neccesary and it seems to work fine, I'll continue checking it to see if its consistent in time. However I paste here the code again, in case someone has the same problem or see something wrong in it.

I don't know how to thank you for your help, you saved me. I wish one day I can return the favor. Thank you very much!

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
 
entity control_unit2 IS
  port (reset: in std_logic;
        clk: in std_logic;
		trigger: in std_logic;
		data : in std_logic_vector (23 downto 0);
        data_out : out std_logic;
        clk_out : out std_logic);
     end control_unit2;
 
Architecture Behavioral of control_unit2 is        
      
   type state_type is (start, load, pulse, rst, shift, check);
      
   signal pstate, nstate : state_type;
   
   signal data_reg : std_logic_vector (23 downto 0);
   
   signal data_next: std_logic_vector (23 downto 0);
   
   signal i_reg : unsigned (4 downto 0);
   
   signal i_next: unsigned (4 downto 0);
   
   signal datout_reg, datout_next: std_logic ;
   
   signal clkout_reg, clkout_next: std_logic;
   
  
       
     BEGIN
     
       
     clocked: PROCESS (clk,reset)
     
     
     BEGIN
	if (reset = '1') then
       
       pstate <= start;
       i_reg <= (others => '0');
       data_reg <= (others => '0');
       datout_reg <= '0';
       clkout_reg <= '0';
       elsif clk'event and clk = '1' then 
       
		pstate <= nstate;
		i_reg <= i_next;
		data_reg <= data_next;
		datout_reg <= datout_next;
		clkout_reg <= clkout_next;
		
		end if;
	end process clocked;
	
	
     states: process(datout_reg, pstate,data,trigger,data_reg,clkout_reg,i_reg)
     
     begin
     
		data_next <= data_reg;
		i_next <= i_reg;
		clkout_next <= clkout_reg;
		datout_next <= datout_reg;
     
		case pstate is
     
			when start =>
				
				if trigger = '1' then
			
					i_next <= to_unsigned(24,5);
					data_next <= data;
					nstate <= load;
					clkout_next <= '0';
				else
			
					nstate <= start;
					
				end if;
			when load => 
			
				datout_next <= data_reg(23);
				nstate <= pulse;
				clkout_next <= '0';
				i_next <= i_reg;
				
				
			when pulse =>
				
				data_next <= data_reg(22 downto 0) & '0';
				clkout_next <= '1';
				nstate <= rst;
				i_next <= i_reg;
				
			when rst => 
			
				i_next <= i_reg;
				clkout_next <= '0';
				nstate <= shift;
				
			when shift => 
			
				i_next <= i_reg - 1;
				 
				nstate <= check;
				
			when check => 
			
				if i_reg = 0 then
				
					nstate <= start;
					
				else 
				
					nstate <= load;
					
				end if;
				
		
			end case;
			
	end process states;
	
	clk_out <= clkout_reg;
	
	data_out <= datout_reg;
	
	
			
			
    END Behavioral;

Pdta: I will read one of those books! Thanks!

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Control shift registers with FPGA

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