Forum Discussion
SKon1
Occasional Contributor
Occasional ContributorContradictions between 2 DDR examples
Hello, In page 12 of this document (Example 1): https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an477.pdf The example lists: Minimum Setup time = 0.9 ns Minimum hold...
SKon1Occasional Contributor
Occasional ContributorThanks sstrell,
In my real life case I'm interfacing my design to an RGMII PHY. The PHY has the internal clock shift function enabled.
I'm attaching the information from the PHY's datasheet.
How would you define the timing constraints in this case ?
